A Single Chip Design and Implementation of Aes -128/192/256 Encryption Algorithms

In this paper an efficient hardware architecture design and implementation of all candidates of AES encryption standards AES-128, AES-192 and AES-256 on the same hardware is proposed. AES algorithm proposed by NIST has been widely accepted as best cryptosystem for wireless communication security. The hardware implementation is useful in wireless security like military and mobile phones. This contribution investigates implementation of AES Encryption with regards to FPGA and VHDL.Optimized and synthesized VHDL code for AES-128, AES-192 and AES-256 for encryption of 128-bit data is implemented. Xilinx ISE 9.2i software is used for simulation. Each algorithm is tested with sample vectors provided by NIST output results are perfect with minimal delay. The proposed design consumes less power and area which is suitable battery driven mobile phones. Throughput reaches the value of 666.67 Mbps for encryption of 128bit data with AES-128 key with FPGA device XC2V6000BF957-6.